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The present invention generally relates to the field of integrated circuit (IC) design, and more specifically, to improved layout verification for standard cells using SPICE.
2. Related Art
Many electronic circuits and devices may be designed using standard cell technology. The standard cell is a type of metal-oxide semiconductor (MOS) transistor that has been pre-designed and pre-synthesized in a library. Standard cells are typically designed using software programs (i.e., computer aided design (CAD) programs) to implement designs of electronic circuits and devices in a simple and convenient manner. The standard cells may be provided by the circuit manufacturer and available as a library of standard cells for use in a particular electronic circuit.
Standard cells are described in U.S. Pat. No. 6,734,545, which issued to Dong et al. on May 4, 2004, U.S. Pat. No. 6,812,135, which issued to Dong et al. on Nov. 2, 2004, and U.S. Pat. No. 7,836,047, which issued to Dong et al. on Nov. 23, 2010. The contents of each of these patents are hereby incorporated herein by reference.
The standard cells are designed to be pre-synthesized and pre-implemented for a particular electronic circuit or device. When the particular electronic circuit or device is designed, a user may use the standard cells to design the particular electronic circuit or device by adding transistor devices in accordance with the standard cell(s). These transistor devices are then coupled to other transistor devices (i.e., the standard cells) of the standard cell(s) to provide the electronic circuit or device with desired functionality.
The transistor devices may be placed and routed in the specific layout of the standard cell(s). However, the routing of the transistor devices can be complicated because the standard
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